In conventional magnetoresistive random access memory (MRAM) devices, the memory cells are typically programmed by magnetic fields induced by current carrying conductor lines such as copper lines or aluminum lines. Typically, two orthogonal interconnects are employed, one positioned above the magnetic memory device and the second positioned below the magnetic memory device. FIG. 1 depicts a conventional MRAM architecture including two conventional conductive lines 10 and 12. The conventional MRAM architecture also includes a memory cell 11, a conductive layer 1100, a conductive stud 8, a ground line 7, a conductive plug 5, and a transistor 13 including a gate 6, a source 3, and a drain 4. The conventional conductor lines 10 and 12 are orthogonal and used for writing data into the conventional magnetic storage element 11. The conventional magnetic storage element 11 shown is a magnetic tunneling junction (MTJ) stack 11 which is located at the intersection of and between conventional conductor lines 10 and 12. Conventional conductor line 10 and conventional conductor line 12 are often referred to as conventional word line 10 and conventional bit line 12, respectively.
The conventional MTJ stack 11 primarily includes a free layer 1104 having a changeable magnetic vector (not shown), a pinned layer 1102 with a fixed magnetic vector (not shown), and an insulator 1103 in between the two magnetic layers 1102 and 1104. Layer 1101, also included in the conventional MTJ stack 11, is usually a composite of seed layers and an anti-ferromagnetic layer that is strongly coupled to the pinned magnetic layer.
During writing, the bit line current in the conventional bit line 12 and word line current through the word line 10 yield two magnetic fields on free layer 1104. In response to is the magnetic fields generated by the bit line and word line currents, the magnetic vector in the free layer 1104 will orient in a direction depending on the direction and amplitude of the bit line and word line current. Generally speaking, writing a zero (0) requires the direction of the bit line current to be different than when writing a one (1). During reading, the transistor 13 is turned on and a small tunneling current flows through the conventional MTJ stack 11. The amount of the current flowing through the conventional MTJ stack 11 or the voltage drop across the conventional MTJ stack 11 is measured to determine the state of the memory cell. In some designs, transistor 13 is replaced by a diode, or completely omitted, and the MTJ stack 11 in direct contact with word line 10.
Although the conventional architecture using the bit line 12 and word line 10 functions, one of ordinary skill in the art will readily recognize that the amplitude of the bit line and word line current is in the order of several milli-ampares for the architecture shown in FIG. 1. A smaller writing current is desired for many memory applications.
FIG. 2 depicts one conventional architecture used to address this issue. The architecture depicted in FIG. 2 contains elements that are analogous to elements in FIG. 1. Consequently, these elements, such as the conventional MTJ stack 11′ and the conventional MTJ stack 11, are labeled similarly. Such conventional architectures are described, for example, in U.S. Pat. Nos. 5,659,499, 5,940,319, 6,211,090, 6,153,443, and U.S. patent application publication Ser. No. 2002/0127743, which describe encapsulating bit lines and word lines with soft magnetic cladding layer on the three surfaces not facing MTJ 11. As shown in FIG. 2, the word line 10 and the bit line 12 are each composed of two parts: the copper core 1001 and 1201, respectively, and the soft magnetic cladding layer 1002 and 1202, respectively. Relative to the conventional architecture in FIG. 1, the soft magnetic cladding layers 1202 and 1002 can concentrate the magnetic flux associated with I1 and I2 onto MTJ stack 11 and reduce the magnetic field on other surfaces which are not facing MTJ stack 11. Experimental data showed that a marked improvement in write efficiency can be achieved using the conventional architecture depicted in FIG. 2.
Although the conventional MRAM architecture shown in FIG. 2 functions, one of ordinary skill in the art will readily recognize that the process of making the conventional MRAM including the lines 10′ and 12′ is extremely complicated. The conventional fabrication process requires 9thin film deposition steps, 5 photolithography steps, 6 etching steps, and 1 chemical mechanical polishing (CMP) step. Furthermore, none of the processes can be shared with other CMOS processes. Moreover, some of the processes, such as the CMP process and a few thin-film deposition and etching processes, need to be tightly controlled in order to achieve the designed performance. In addition to cost concerns, the complicated fabrication processes pose significant challenge to scaling to higher densities.
Accordingly, what is needed is a system and method for providing an improved MRAM architecture having simpler fabrication as well as improved performance. The present invention addresses such a need.